Characterization of Semiconductor Materials at Sub-Micron Scale Using Scanning Capacitance Microscopy
Takayuki UCHIHASHI, Yoshimori ISHIZUKA, Haruhiko YOSHIDA and Seigo KSIHINO
Abstract:A scanning capacitance microscope (SCM) has been implemented by fabricating a contact-mode atomic force microscope (AFM) with a high-sensitive capacitance sensor. The SCM has promise as next-generation characterization technique of electrical properties such as interface traps in metal-oxide-semiconductor (MOS) devices and carrier density because the measurement is inherently two dimensional with high spatial resolution at a nanometer scale. We demonstrate differential capacitance and capacitance images of the p-n junction on a Si wafer induced by different dopant density. Also we show SCM images due to negatively trapped charges in a Si02 film, which are injected from the conductive probe tip. The resulting shift in differential capacitance (dC/dV) versus voltage (V) curves due to the locally trapped charge was measured by the high-frequency dC/dV-V measurement. Finally, we applied the SCM to characterization of a cross-sectional surface of a silicon-on-insulator (SOI) wafer. The SCM images identified the depletion layer at the SOI/buried oxide (BOX) interface, and the thickness of the depletion layer was found to vary according to the bias voltage applied to the Si substrate. These results represent that the SCM is a promising tool for sub-micron-scale electrical characterization of not only a bulk Si wafer but also a SOI wafer. Key Words:Scanning capacitance microscope, Semiconductor, Silicon-on-insulator, Electrical characterization